1. Field of the Invention
This invention relates to a pulse delay circuit device which is so designed that the delay time and pulses width of an output pulse can be set up as desired and which is adapted for processing high-speed input pulse and thus can be most effectively employed for timing adjustment of logic circuit device such as computer or the like, for example.
2. Description of the Prior Art
Generally, a conventional variable delay circuit employs a variable delay line constituted by coils and capacitors. However, such an arrangement is disadvantageous in that its large external size leads to a low packaging density. A further disadvantage is such that satisfactory charactertistics cannot always be achieved with respect to high-speed input pulse. Among the conventional variable delay circuits are one of the type in which a tap is mechanically switched to adjust the delay time; one of the type in which a tap is switched by means of a multiplexer; one of the type in which the delay time is adjusted by means of a slider, and so forth. However, the last-mentioned type is disadvantageous in that it requires that fine delay time adjustment be effected by moving the slider through the use of a jig. With the conventional variable delay lines, therefore, troublesome adjustment steps are involved, and a number of other steps are needed. Another disadvantage is such that great difficulty is encountered in an attempt to set up the width of output pulse as desired.
Delay circuits using transistors are disadvantageous in that difficulty is experienced in adjusting the width of output pulse as is the case with the above-mentioned types of variable delay lines; a high switching speed is difficult to achieve; and a complex circuit arrangement is required in an attempt to effect adjustment of pulse width.